• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A buffered direct injection pixel comprising a photodiode to receive an input signal, a direct injection transistor associated with the photodiode, and a Sackinger current mirror coupled to the direct injection transistor, providing reduced size, low noise and low power consumption compared to the prior art buffered direct injection pixel.
    公开号:BE1021861B1
    申请号:E2014/0481
    申请日:2014-07-02
    公开日:2016-01-22
    发明作者:Lin Minlong
    申请人:Sensors Unlimited Inc.；
    IPC主号:
    专利说明:

    PIXEL WITH DIRECT INJECTION IN BUFFER MEMORY FOR INFRARED DETECTOR ARRAYS
    BACKGROUND OF THE INVENTION 1. Field of the invention
    The present invention relates to an image sensor circuit and, more particularly, a buffered direct injection pixel circuit for an infrared focal plane array, having the characteristics of reduced size, low noise and low power consumption. . 2. Background of the related art
    Infrared detector systems typically require sophisticated tracking algorithms to accommodate the large and frequent variations in background information that result from the relatively high contrast and solar component of the radiation. However, detectors operating in the infrared (IR) spectral band can achieve the same or greater thermal sensitivity with reduced complexity of signal processing. As a result, infrared detection and tracking can often be accomplished by using smaller, more cost effective sensors with IR FPAs.
    Unfortunately, IR focal plane arrays and multiplexing readout circuits have design constraints that can severely limit system performance. In the read portion of an APF, for example, the input amplifier cell circuit that couples each photodetector to the corresponding reading site must perform several functions that are difficult to incorporate simultaneously in the small amount of space or "place" that is usually available on a signal processing chip.
    A detector / amplifier cell of an APF should ideally include: a detector interface stage that provides a low impedance at a uniform operating bias; a large load processing integration capability; a floor for the uniform suppression of the background if the integration capacity is inadequate; low power multiplexing and resetting stages; and an output stage adapted to control the bus line capability for successive multiplexing at video rates.
    The prior art FPA IRs generally lack impedance buffering, which causes a change in the detector dark currents and an increase in fixed pattern noise (i.e., the remaining space noise). after applying a conventional two-point non-uniformity correction). Fixed pattern noise creates a visible mask in imaging that hides high-frequency and low-contrast information, thereby degrading the minimum detectable temperature and compromising performance under adverse conditions. Furthermore, the devices of the prior art lack the ability to reduce the pitch of the pixels and increase the density of the pixels. If pixel pitch and room for sensor / amplifier cells are reduced in the prior art devices, the performance limitations are further enhanced. As pixel pitch continues to decrease, power and noise issues become even more daunting.
    Given the current state of the art and the limited available chip area, there is insufficient room for detector / amplifier cells for a read circuit with conventional architecture to incorporate all of the most important features such as low input impedance, uniform polarization of the detector and satisfactory charge storage capacity. However, since small cells are required for FPAs with large numbers of pixels, integrated read circuits with reasonable chip sizes, and compact optics, all important functions of the read circuit must be integrated in one place. cell as small as possible. Thus, there is a need for a pixel reading circuit with improved architecture having features that are better optimized for use in an IR FPA.
    SUMMARY OF THE INVENTION
    The present invention relates to a new buffered direct injection (BDI) pixel useful for an infrared (IR) focal plane array (FPA) sensor. The BDI pixel comprises a photodiode for receiving an input signal, a direct injection transistor associated with the photodiode, and a low power Sackinger current mirror coupled to the direct injection transistor and comprising only two transistors. There are two different pixel configurations considered, each having a different polarity.
    In one configuration, the BDI pixel direct injection transistor is a PMOS transistor, and the Sackinger current mirror comprises a grounded bias transistor. Thus, an embodiment of the present BDI pixel comprises two PMOS transistors and an NMOS transistor.
    In another configuration, the direct injection transistor of the BDI pixel is an NMOS transistor, and the Sackinger current mirror comprises a bias transistor connected to a power source. Thus, another embodiment of the present BDI pixel comprises a PMOS transistor and two NMOS transistors.
    In both embodiments, the direct injection transistor is coupled to a pixel circuit via an integrating capacitor. The pixel circuit includes three transistors, including a line select transistor, a source follower transistor, and a reset transistor.
    Thus, in both cases, the BDI pixel circuit of the present invention comprises a total of six transistors, resulting in a reduced circuit architecture, low noise, and low power consumption, compared to direct injection pixel of the prior art.
    These features of the BDI pixel of the present invention and others will become more apparent from the detailed description hereinafter made with reference to the accompanying drawings.
    BRIEF DESCRIPTION OF THE DRAWINGS
    In order to make it easier for those skilled in the art to understand how to realize the buffered direct injection pixel circuit described herein, aspects thereof will be described in detail below with reference to the drawings. wherein: Figure 1 is a schematic representation of an embodiment of the buffered direct injection pixel circuit of the present invention, wherein the direct injection transistor is a PMOS transistor and the mirror bias transistor Sackinger current is connected to ground; and Figure 2 is a schematic representation of another embodiment of the buffered direct injection pixel circuit of the present invention, wherein the direct injection transistor is an NMOS transistor and the mirror polarization transistor of the present invention. Sackinger current is connected to a power source.
    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    Referring now to the drawings in which like reference numerals identify similar structural aspects or elements of the present invention, in Figures 1 and 2 are illustrated new embodiments of a buffered direct injection pixel ( BDI) for an infrared (IR) focal plane matrix (FPA) sensor.
    Referring to Figure 1, there is shown a Buffered Direct Injection (BDI) pixel cell of the present invention, indicated generally by reference numeral 10. The BDI pixel cell 10 comprises a photodiode 12 of the present invention. any type or substrate for receiving an input signal, such as photons from an IR radiation source.
    The photodiode 12 converts the input signal into an electrical signal. A direct injection transistor 14 is associated with the photodiode 12 and reads the electrical signal from it. In this embodiment, the direct injection transistor is a p-type MOSFET transistor, also called a PMOS transistor.
    The direct injection PMOS transistor 14 is coupled to a two-transistor Sackinger current mirror, generally identified by reference numeral 16. The two-transistor Sackinger current mirror 16 replaces a full five-transistor pixel amplifier. used in pixel cells of the prior art. As a result, the Sackinger 16 current mirror consumes a very small amount of current, for example less than about current InA, compared to a current consumption of about 50nA-100nA for a conventional pixel amplifier. Those skilled in the art should readily appreciate that a current mirror is designed to copy a current through an active device by controlling the current in another active device, keeping the output current constant regardless of the load. From a conceptual point of view, an ideal current mirror is simply an ideal inverter current amplifier that reverses the direction of the current.
    The Sackinger current mirror 16 includes first and second transistors 18 and 20. The first transistor 18 is a PMOS transistor and is connected to a power source. The second transistor 20 is an NMOS transistor, which acts as a bias transistor for the current mirror 16, and is connected to ground. Thus, the BDI10 pixel comprises two PMOS transistors and an NMOS transistor.
    Still with reference to FIG. 1, the direct injection transistor 14 of the BDI pixel cell 10 is coupled to a conventional pixel circuit 22 through an integration capacitor 24. The integration capacitor 24 operates for converting the input signal from the photodetector 12 into a voltage. Those skilled in the art will readily appreciate that the integration capacitor 24 is optional in this circuit architecture.
    The pixel circuit 22 has three transistors, including a reset transistor 26, a line select transistor 28, a source follower transistor 30, each of which is well known in the art. Those skilled in the art will readily appreciate that the pixel circuit 22 may take the form of any other known pixel read circuit architecture. Furthermore, the scope of the present invention should not be unduly limited to the illustrated architecture of the pixel circuit 22.
    Referring to Figure 2, there is shown another Buffered Direct Injection (BDI) pixel cell of the present invention, generally identified by reference numeral 100. The BDI pixel cell 100 comprises a photodiode 112 of any type or substrate for receiving an input signal. The photodiode 112 converts the input signal into an electrical signal.
    A direct injection transistor 114 is associated with the photodiode 112 and reads the electrical signal from it. In this embodiment, the direct injection transistor is an n-type MOSFET transistor, also called NMOS transistor.
    The forward injection NMOS transistor 114 is coupled to a two-transistor Sackinger current mirror, indicated generally by reference numeral 116. The Sackinger current mirror 116 is of a different polarity from that of the current mirror. Sackinger 16 of Figure 1. Therefore, the first transistor 118 of the Sackinger 116 current mirror is an NMOS transistor which acts as a bias transistor and is connected to a power source. The second transistor 120 is a PMOS transistor that is connected to ground. Thus, the BDI pixel cell 100 comprises a PMOS transistor and two NMOS transistors.
    Still with reference to FIG. 2, the direct injection transistor 114 of the BDI pixel cell 100 is coupled to a conventional pixel circuit 122 through an integrating capacitor 124. The pixel circuit 122 has three transistors, comprising a reset transistor 126, a line select transistor 128 and a source follower transistor 30, each of which is well known in the art. Those skilled in the art will readily appreciate that the pixel circuit 122 may take the form of any other known pixel read circuit architecture. Furthermore, the scope of the present invention should not be unduly limited to the illustrated architecture of the pixel circuit 122.
    In both embodiments of the present invention, the BDI pixel circuit of the present invention comprises a total of six transistors, resulting in a reduced-size circuit architecture covering less "space", compared to pixel circuits. direct injection system of the prior art comprising a five transistor pixel amplifier.
    Furthermore, the BDI pixel cell of the present invention consumes less than 1% of the power consumed by a pixel cell made with a conventional five transistor pixel amplifier. Thus, a much larger pixel array can be constructed using the BDI pixels of the present invention. There is also lower noise generated by the BDI pixels of the present invention, compared to the conventional BDI pixel.
    More particularly, with a smaller pixel pitch, the signal irradiation per pixel inevitably decreases and the signal-to-noise ratio decreases accordingly. Indeed, a lower number of transistors and a low bias current in this embodiment contribute to a lower noise compared to the read design in the prior art.
    In addition, the Sackinger current mirror provides much less variation in the reverse bias of the photodiode by its intrinsic negative feedback. This is similar to a conventional direct injection six-channel pixel amplifier, but with much less space, power, and noise.
    Although the present invention has been described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and modifications can be made thereto without departing from the spirit and scope of the present invention. present invention as defined by the appended claims.
    权利要求:
    Claims (20)
    [1]
    A buffered direct injection pixel comprising: a current mirror coupled to a direct injection transistor.
    [2]
    The buffered direct injection pixel of claim 1, further comprising a photodiode associated with the direct injection transistor for receiving an input signal to the pixel.
    [3]
    The buffered direct injection pixel of claim 1, wherein the direct injection transistor is a PMOS transistor.
    [4]
    The buffered direct injection pixel of claim 1, wherein the direct injection transistor is an NMOS transistor.
    [5]
    The buffered direct injection pixel of claim 1, wherein the current mirror is a Sackinger current mirror which consumes less than about current InA.
    [6]
    The buffered direct injection pixel of claim 3, wherein the current mirror comprises a bias transistor connected to ground.
    [7]
    The buffered direct injection pixel of claim 4, wherein the current mirror comprises a bias transistor connected to a power source.
    [8]
    The buffered direct injection pixel of claim 1, wherein the direct injection transistor is coupled to a pixel circuit.
    [9]
    The buffered direct injection pixel of claim 8, wherein the direct injection transistor and the pixel circuit are coupled through an integrating capacitor.
    [10]
    The buffered direct injection pixel of claim 9, wherein the pixel circuit comprises a line selection transistor.
    [11]
    The buffered direct injection pixel of claim 10, wherein the pixel circuit further comprises a source follower transistor.
    [12]
    The buffered direct injection pixel of claim 11, wherein the pixel circuit further comprises a reset transistor.
    [13]
    A buffered direct injection pixel comprising: a) a photodiode for receiving an input signal; b) a direct injection transistor associated with the photodiode; and c) a Sackinger current mirror which consumes less than about current InA coupled to the direct injection transistor.
    [14]
    The buffered direct injection pixel of claim 13, wherein the direct injection transistor is a PMOS transistor.
    [15]
    The buffered direct injection pixel of claim 13, wherein the direct injection transistor is an NMOS transistor.
    [16]
    Buffered direct injection pixel according to claim 14, wherein the Sackinger current mirror comprises a bias transistor connected to ground.
    [17]
    The buffered direct injection pixel of claim 15, wherein the Sackinger current mirror comprises a bias transistor connected to a power source.
    [18]
    The buffered direct injection pixel of claim 13, wherein the direct injection transistor is coupled to a pixel circuit.
    [19]
    The buffered direct injection pixel of claim 18, wherein the direct injection transistor is coupled to the pixel circuit through an integrating capacitor.
    [20]
    The buffered direct injection pixel of claim 19, wherein the pixel circuit comprises a line select transistor, a source follower transistor, and a reset transistor.
    类似技术:
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
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    US13/936,533|US9191586B2|2013-07-08|2013-07-08|Buffered direct injection pixel for infrared detector arrays|
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